1. Field of the Invention
The embodiments of the invention generally relate to integrated circuit analysis and, more particularly, to a system and method for computing a value of a particular attribute of an integrated circuit based on accumulated results of data analysis from sample windows, where the sample windows are selected from the integrated circuit layout using an open deterministic sequencing technique.
2. Description of the Related Art
In the past the techniques used to analyze the layout and/or electrical properties of an integrated circuit often entailed analyzing the entire chip and not samples thereof. For example, Voronoi-based techniques are often used to map out a full-chip and compute the critical area defect mechanisms on the chip (e.g., as illustrated in the following U.S. patents and Published U.S. patent applications incorporated herein by reference: U.S. Pat. No. 6,044,208 issued to Papadapoulou et al. on Mar. 28, 2000; U.S. Pat. No. 6,718,539 issued to Papadapoulou et al. on Jan. 23, 2001; U.S. Pat. No. 6,247,853 issued to Papadapoulou et al. on Jun. 19, 2001; U.S. Pat. No. 6,317,859 issued to Papadapoulou et al. on Nov. 13, 2001; U.S. Pat. No. 7,143,371 issued to Allen et al. on Nov. 28, 2006; U.S. Patent Application Publication No. 2005/0240839 of Allen et al. published Oct. 27, 2005; and U.S. Patent Application Publication No. 2006/0150130 of Allen et al. published Jul. 6, 2006). However, as technology advances and design size increases full-chip analyses have become prohibitively time-consuming.